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TDA7326 am-fm radio frequency synthesizer fm input and precounter for up to 140mhz am input for up to 40mhz 6-bit swallow counter, 8-bit pro- grammable counter for fm and sw 14-bit programmable counter for lw and mw three wires 8-bit serial interface on-chip reference oscillator and counter programmable scanning steps for am and fm digital phase detector and loop fil- ter two separate free programmable filter applications available tuning voltage output 0.5 to 9.5v programmable current sources to set the loop gain on-chip power on reset standby mode description the TDA7326 is a pll frequency synthesizer in cmos technology that performs all the function of a pll radio tuning system for fm and am (lw, mw, sw) july 1994 block diagram ordering numbers: TDA7326 (dip16) TDA7326d (so16w) so16w dip16 1/16
absolute maximum ratings symbol parameter value unit v dd1 -v ss supply voltage - 0.3 to + 7 v v dd2 -v ss supply voltage - 0.3 to + 12 v v in input voltage vss - 0.3 to v dd + 0.3 v v out output voltage vss - 0.3 to v dd + 0.3 v i in input current - 10 to + 10 ma i out output current - 10 to + 10 ma t stg storage temperature - 55 to + 125 o c t a ambient temperature -40 to + 85 o c thermal data symbol parameter dip 16 so 16l unit r th j-amb thermal resistance junction-ambient 100 200 c/w pin connection figure 1: input sensitivity TDA7326 2/16
electrical characteristics (t amb =25 c;v dd1 = 5v; v dd2 =9vf osc = 4mhz; r iset = 68k w ; unless otherwise specified.) symbol parameter test condition min. typ. max. unit v dd1 supply voltage 4.5 5.0 5.5 v v dd2 supply voltage 9.0 10.0 v i dd1 fm supply current no output load, fm mode, f in = 100mhz 10 18 25 ma i dd1 am supply current no output load, am mode, fin = 1mhz 3 5 10 ma i dd1 stb supply current standby mode 3 20 m a i dd2 supply current 0.5 2 3 ma v ref voltage at pin 3 3.0 3.5 4.0 v v iset voltage at pin 2 riset = 68k w 7.0 8.0 9.0 v rf input (amin fmin) f iam input frequency am direct mode, v in = 50mv 0.5 20 mhz swallow mode, v in = 50mv 16 40 mhz f ifm input frequency fm sinus, v in = 50mv 30 140 mhz v iam input voltage am direct mode 0.6 to 16mhz (sinus) 40 600 mvrms swallow mode 16 to 40mhz (sinus) 40 600 mvrms v ifm input voltage fm 70 to 120mhz (sinus) 30 600 mvrms z in input impedance fm fin = 120mhz 200 w z in input impedance am fin = 12mhz 1400 w oscillator f osc oscillator frequency 4 mhz t bu built up time euro-quartz itt 100 ms c in internal capacitance 9 pf c out internal capacitance 9 pf z in input impedance 4 15 k w v in input voltage 0.5 v dd1 vpp pll characteristics f step step width am 1/2.5 khz f step step width fm 12.5/25 khz f ref ref frequency am 1/2.5 khz f ref ref frequency fm 12.5/25 khz loop filter input (lp in1 ,lp in2 = pin 15,16) -i in input leakage current vin = v ss ; phase detector output = tristate -1 -0.1 m a i in input leakage current vin = v dd ; phase detector output = tristate 0.1 +1 m a TDA7326 3/16
electrical characteristics (continued) loop filter output (lp out = pin 14) symbol parameter test condition min. typ. max. unit v ol output voltage low iload = 0.2ma v dd2 ; = 10v 0.5 0.8 v v oh output voltage high -iload = 0.2ma v dd2 ; = 10v 9 9.5 v charge pump current generation (lp in1 ,lp in2 = pin 15, 16) i si sink current lpin1,2 curr1 = 0, curr2 = 0 2 5 7 m a curr1 = 0, curr2 = 1 120 200 280 m a curr1 = 1, curr2 = 1 180 300 420 m a curr1 = 1, curr2 = 0 370 500 630 m a -i so source current lpin1,2 curr1 = 0, curr2 = 0 2 5 7 m a curr1 = 0, curr2 = 1 120 200 280 m a curr1 = 1, curr2 = 1 180 300 420 m a curr1 = 1, curr2 = 0 370 500 630 m a dout1 opendrain output (pin 9) v ol output voltage low iload = 1ma 0.2 0.5 v bus interface -i il input leakage current vin = v ss -1 0.1 1 m a i ih input leakage current vin = v ss -1 0.1 1 m a v ih input voltage high leading edge 3.4 4.0 v v il input voltage low leading edge 1.0 1.6 v bus interface, waiting time (see fig. 5) the data is acquired at the high low clock transition t 1 clk low to dlen l h 0.2 m s t 3 data transition to clk h l 0.1 m s t 5 clk h l to data transition 0.4 m s bus interface, data repetition time (see fig. 5) t r1 release time between 2 bytes, except byte 4 5 m s t r2 release time after the transmission of byte 4 fm mode 180 m s am mode 2 ms bus interface, setup time (see fig. 5) t 2 dlen high to clk l h 0.1 m s bus interface, hold time (see fig. 5) t 4 data transition to ckl l h0 m s t 6 clk h l to dlen h l 0.4 m s f clk clk frequency 500 khz duty cycle 50 % t pl clock pulse low 1 m s t ph clock pulse high 1 m s TDA7326 4/16
2.0 general description this circuit contains a frequency synthesizer and a loop filter for an fm and am radio tuning sys- tem. only a v co is required to build a complete pll system. for fm and sw application, the counter works in a two stages configuration. the first stage is a swallow counter with a four modulus (:32/33/64/65) precounter. the second stage is an 8-bit programmable counter. for lw and mw application, a 14-bit programma- ble counter is available. the circuit receives the scaling factors for the pro- grammable counters and the values of the refer- ence frequencies via a three line serial bus inter- face. the reference frequency is generated by a 4mhz xtal oscillator followed by the reference divider. an external oscillator (f = 4mhz) can be used in- stead of the internal one; it must be connected to oscin (pin 7). the reference step-frequency is 1 or 2.5khz for am. for fm mode a step frequency of 12.5 and 25khz can be selected. the circuit checks the format of the received data words. valid data in the interface shift register are stored automatically in buffer registers at the end of transmission. the output signals of the phase detector are switching the programmable current sources. their currents are integrated in the loop filter to a dc voltage.the values of the current sources are programmable by two bits also received via the serial bus. the loop filter amplifier is supplied by a separate positive power supply, to minimize the noise in- duced by the digital part of the system. the loop gain can be set for different conditions. after a power on reset, all registers are reset to zero and the standby mode is activated. in standby mode, oscillator, reference counter, am input and fm input are stopped. the power consumption is reduced to a minimum. 3.0 detailed description of the pll frequency synthesizer 3.1 input amplifiers the signals applied on am and fm input are am- plified to get a logic level in order to drive the fre- quency dividers. 3.1.1 input impedance the typical input impedance: for the fm input is 200 w and for am input is 1.4k w . 3.1.2 input sensitivity (see figures 1a and 1b). 3.2 data and control register 3.2.1 register location the data registers (bit2...bit7) for the control register and the data registers pc7...pc0, sc5...sc0 for the counters are organized in four words, identified by two address bits (bit 7 and bit 6), bit 7 is the first bit to be sent by the controller, bit0 is the last one. the order and the number of the bytes to be transmitted is free of choice. the modification of the pc7...pc0 registers is valid for the internal counters only after transmission of byte 4 (sc5...sc0) . address bits data bits byte msb-bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb bit 0 function adr 0 adr 1 data 0 data 1 data 2 data 3 data 4 data 5 byte 1 0 0 test 0 test 1 test 2 sout curr2 f ref byte 2 0 1 pc7 pc6 lpf1/2 curr 1 swm/dir am/fm byte 3 1 0 pc5 pc4 pc3 pc2 pc1 pc0 byte 4 1 1 sc5 sc4 sc3 sc2 sc1 sc0 3.2.2 control and status registers register configuration register name function swm/dir swallow direct-mode switch 1 = swm, 0 = dir am/fm am - fm band switch 1=am, 0 = fm f ref selection of reference frequency (see table 3.4) curr1 current select of change pump curr2 current select of change pump lpf1/lpf2 loop filter input select 1= i pf1 ,0=i pf2 sout switch output condition 1=output high, 0 = output low TDA7326 5/16
3.3 divider from v co frequency to reference frequency this divider provides a low frequency f syn which is phase compared with the reference frequency f ref . 3.4 operating mode four operating modes are available: - fm mode, - am swallow mode, - am direct mode, - standby mode they are user programmable with the swr/dir and am/fm bits in the byte 2. standby mode: all functions are stopped. this al- lows low current consumption without lost of infor- mation in all register, it is activated by forcing bit 0 (am/fm) and bit 1 (swm/dir) both at zero value. 3.4.1 fm and am (sw) operation (swallow mode) the fm or am signal is applied to a four modulus: 32/33/64/65 high speed prescaler, which is controlled by a 6 bit divider 'a'.this divider is controlled by the 6 bit sc register. in parallel the output of the prescaler is con- nected to a 8 bit divider 'b'. this divider is controlled by the 8 bit pc register. for fm mode with 25khz reference frequency opera- tion, the divider a is a 5 bit divider. the high speed prescaler is working in : 32/33 dividing mode. bit 6 of the sc register has to be kept to o0o. dividing range calculation : for fm mode with 12.5khz reference fre- quency and sw swallow mode operation : f vco =[65 ? a 1 +(b 1 +1 -a 1 ) ? 64 ] . f ref or important : for correct operation b 64 and b a. at fm mode with 25khz reference frequency : f vco =[33 ? a 2 +(b 2 +1-a 2 ) ? 32 ] ? f ref important: for correct operation b 32 and b a. a and b are variable values of the dividers. to keep the actual tuning frequency after a modification of the reference frequency, the values of the dividers have to be modified in the following way. switching from 25khz to 12.5khz reference frequency : b 1 =b 2 ,a 1 =a 2 ? 2 switching from 12.5khz to 25khz reference frequency: b 2 =b 1 ,a 2 = a 1 2 and a 2 = ( a 1 + 1 ) 2 for odd values a 1 . the am signal is directly applied to the 14 bit static divider 'c'. this divider is controlled by both sc and pc registers. dividing range: predivider r osc in register sc5 .. sc0 counter a predivider m/m+1 am in fm in register pc7 .. pc0 counter b pd fref fsyn d94au101 figure 2: fm and am (sw) operation (swallow mode) mode section swm/dir am/fm stand-by 0 0 fm 1 0 am swallow 0 1 am direct 1 1 f vco = (64 ? b 1 +a 1 + 64) ? f ref f vco = (32 ? b 2 +a 2 + 32) ? f ref f vco =(c+1) ? f ref TDA7326 6/16
3.4 reference frequency generator the crystal oscillator clock is divided by the reference frequency divider to provide the ref- erence frequency to the phase comparator. reference frequency divider range is select- able by the programming bit 'f ref '. available reference frequency are shown in following table. predivider r osc in register pc7 .. pc0 counter : c am in fm in register sc5 .. sc0 pd fref fsyn d94au102 msb figure 3: am direct mode operation for sw, mw and lw figure 4: phase comparator am/fm f ref f ref (khz) 0 0 12.5 0125 101 1 1 2.5 table 3.4 TDA7326 7/16
dlen clk data t1 t2 tph tpl t r1 t3 t5 t4 byte 1 - 3 byte 4 byte 1 - 3 byte 1 - 4 d94au103 figure 5 TDA7326 8/16
3.5 three state phase comparator the phase comparator generates a phase error signal according to phase difference between f syn and f ref . this phase error signal drives the charge pump current generator 3.6 charge pump current generator this system generates signed pulses of current. duration and polarity of those pulses are deter- mined by the phase error signal. the absolute current values are programmable by 'curr1' and 'curr2' bits and controlled by an external resistor r iset connected to pin 2 and gnd. 3.7 low noise cmos op-amp a low noise op-amp is available on chip. the positive input of this op-amp is connected to an internal voltage divider and to pin 3 'v ref '. the negative input is connected to the charge pump output. in cooperation with this internal amplifier and external components, an active filter can be provided. to increase the flexibility in application the negative input can be switched to two input pins (pins 15 and 16). this switch is controlled by 'lpf' register with 'lpf' low pin 15 is active and 'lpf' high pin 16 is active. this feature allows two separate active filters with different perform- ance. 3.8 test function the test pin (test out) is used only for testing: it has no use in real applications. the three bits test0, test1, test2, of the test register must be programmed as 0,0,0 in application. some device internal signals can be checked at pin 9 (tst out) and pin 7 (osc in) by program- ming different codes of the test register according to the table 1. for example by programming the code 110 the ofsyn outo will be available at pin 9 and of ref in- puto at pin 7. 3.9 c-bus interface this interface allows communication between the pll device and m p systems. a bus control system check the format of transmission, only eight bit word transmission is allowed. four registers with 6 bit are user programmable. the selection of this four registers is controlled by two address bits. test register status test function test 0 test 1 test 2 pin9 (test/out) pin 7 (oscin) 000s out (appl. mode) o scin (appl. mode) 100 f ref output o scin (appl. mode) 010 p hi output f ref input 110 f syn output fref input 001 p hi input o scin (appl. mode) table 1: TDA7326 9/16
5.0 frequency programmation 5.1 am/fm computation resume where: pc = program counter value (pc7 to pc0) sc = swallow counter value (sc5 to sc0) div_val = divider factor loading registers for 11 or 12 bits of the programmable counters 1 0 pc5 pc4 pc3 pc2 pc1 pc0 1 1 sc5 (0)* sc4 sc3 sc2 sc1 sc0 loading registers for 5 or 6 bits of the programmable counters 11 sc5 (0)* sc4 sc3 sc2 sc1 sc0 setting control register for loop filter selection charge pump current bit 1, mode am/fm selection 01xx lpf2/ lpf1 curr1 swm/ dir am fm test mode inizialization (test0 = test1 = test2 = 0) 0 0 tst0 tst1 tst2 s out curr2 f ref setting control register for switch output pin 9, charge pump current bit 2, reference frequency select 00000s out curr2 f ref (*) this bit has to be o0o for f ref =o1o(f ref = 25khz in fm mode or 2.5khz am swallow mode) loading registers for all bytes of the programmable counters and all control registers 0 1 pc7 pc6 lpf1/ lpf2 curr1 swm dir am fm 1 0 pc5 pc4 pc3 pc2 pc1 pco ? ? 11 sc5 (0)* sc4 sc3 sc2 sc1 sc0 0 0 0 0 0 s out curr2 f ref 4.0 bit organization of the bus transfer operation loading registers for all bytes of the programmable counters and all control registers 0 1 pc7 pc6 lpf2/ lpf1 curr1 swm dir am fm 1 0 pc5 pc4 pc3 pc2 pc1 pco ? ? 11 sc5 (0)* sc4 sc3 sc2 sc1 sc0 f ref = 12.5khz f vco = (64 ? pc + sc + 64) ? f ref fm swallow mode f vco = (div_val+ 64) ? f ref swallow 6bit f ref = 25khz f vco = (32 ? pc + sc + 32) ? f ref f vco = (div_val+ 32) ? f ref swallow 5bit (bit sc5 = 0) TDA7326 10/16
f ref = 1khz f vco = (64 ? pc + sc + 64) ? f ref am swallow mode f vco = (div_val+ 64) ? f ref swallow 6bit f ref = 2.5khz f vco = (32 ? pc + sc + 32) ? f ref f vco = (div_val+ 32) ? f ref swallow 5bit (bit sc5 = 0) am direct mode f vco = (div_val+ 1) ? f ref a) conditions: fm mode (f rf = 98.1mhz, f ref = 25khz; if = 10.7mhz it follows: that f vco = 98.1 + 10.7 = 108.8mhz div_val = f vco f ref - 32 =4352 - 32 = 4320 = 10 e 0 hex = 5.2: examples 10000111000000 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 sc5 sc4 sc3 sc2 sc1 sc0 sc = 0 (*) binary ? pc = 135 b) conditions: fm mode (f rf = 98.8mhz, f ref = 25khz; if = 10.7mhz it follows: f vco = 98.8 + 10.7 = 109.5mhz div_val = 4380 - 32 = 4348 = 10 fc hex = 10000111011100 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 sc5 sc4 sc3 sc2 sc1 sc0 sc = 28 (*) binary ? pc = 135 note: (*) the bit sc5 is forced = 0, and higher weigth bits are left shift ed one position. TDA7326 11/16
d) conditions: am direct mode, (f rf = 530khz, f ref = 1khz; if = 450khz it follows: f vco = 530 + 450 = 980khz div_val = f vco f ref 1 = 980 1 1 = 979 = 3d3 hex = 00001111010011 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 sc5 sc4 sc3 sc2 sc1 sc0 binary e) conditions: am direct mode, (f rf = 1710khz, f ref = 1khz; if = 450khz it follows: f vco = 1710 + 450 = 2160khz div_val = f vco f ref 1 = 2160 1 1 = 2159 = 86f hex = 00100001101111 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 sc5 sc4 sc3 sc2 sc1 sc0 binary c) conditions: fm mode (f rf = 98.8mhz, f ref = 12.5khz; if = 10.7mhz it follows: f vco = 98.8 + 10.7 = 109.5mhz div_val = 8760 - 64 = 8696 = 21 f8 hex = 10000111111000 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 sc5 sc4 sc3 sc2 sc1 sc0 sc = 56 binary ? pc = 135 TDA7326 12/16
figure 5: application with two loop-filters *) c7 must be connected as closed as possible between pin 10 and pin 13 figure 6: pc board and component layout of fig. 5 TDA7326 13/16
dip16 package mechanical data dim. mm inch min. typ. max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 TDA7326 14/16
so16 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.012 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 10.1 10.5 0.398 0.413 e 10.0 10.65 0.394 0.419 e 1.27 0.050 e3 8.89 0.350 f 7.4 7.6 0.291 0.299 l 0.5 1.27 0.020 0.050 m 0.75 0.030 s8 (max.) TDA7326 15/16
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications men- tioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. TDA7326 16/16

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